System and Method for Balancing Current of Converter Phases

ABSTRACT

Systems and methods for balancing phase currents of the phases of a multiphase converter include alternately connecting the phases during respective intervals to an input current and sampling, at a node of the multiphase converter that is common to the phases, the input current provided to the phases to obtain respective input current samples for the phases. While the input current samples are unequal, the intervals are adjusted to minimize inequality of the input current samples and thereby balance the phase currents.

TECHNICAL FIELD

The present invention relates to balancing phase currents of amultiphase converter.

BACKGROUND

A DC/DC converter converts an input DC voltage to an output DC voltage.The converter includes at least one converter circuit which functionsfor the converter to convert the input voltage to the output voltage. A“multiphase” converter includes multiple converter circuits. Eachconverter circuit forms a respective “phase” of the converter.

In operation for the converter to convert an input voltage to an outputvoltage, a controller switches on the phases at respective intervalsover successive switching periods. The intervals are spaced-apart suchthat only one phase is switched on at a time. Current from the input ofthe converter flows to a phase while the phase is switched on.

Under the assumption that the electrical components of the phases havethe same component values, the controller switches the phases on withthe same duty cycle. Consequently, the phases will have the samecurrents when the components have the same component values.

However, due to the component values differing from tolerance and/orageing, the behavior of the phases differs, and the phases will havedifferent currents. Traditionally, then, one current-loop control isdefined per each phase (i.e., individually controlling each phasecurrent). This, however, requires high CPU processing load at thecontroller and a greater number of components (e.g., each phase ismodified to include its own power shunt and operational amplifier).

It is desirable, then, to have a common, single current loop for allphases. This is to reduce the cost and the CPU load. But, with a commoncurrent control, differences in the phases lead to unbalanced phasecurrents. This results in overstress in the phases that are deliveringmore current, thus reducing the total converter life.

SUMMARY

A method for balancing phase currents of a plurality of phases of amultiphase converter is provided. The method includes alternatelyconnecting the phases during respective intervals to an input currentand sampling, at a node of the multiphase converter that is common tothe phases, the input current provided to the phases to obtainrespective input current samples for the phases. While the input currentsamples are unequal, the intervals are adjusted to minimize inequalityof the input current samples.

The method may further include generating trigger signals at successivetime instants respectively for the phases and sampling the input currentprovided to the phases occurs at the time instants in response to thetrigger signals. Generating the trigger signals may includesynchronizing the trigger signals such that a time instant of a triggersignal for a first one of the phases occurs while the first one of thephases is connected to the input current and a time instant of a nextsucceeding trigger signal for a second one of the phases occurs whilethe second one of the phases is connected to the input current.

The node of the multiphase converter that is common to the phases may beconnected to a DC-link capacitor of the multiphase converter.

Adjusting the intervals may include increasing the interval for a phasehaving an input current sample lower than an average of the inputcurrent samples to increase the input current provided to the phase.Adjusting the intervals may also include decreasing the interval for aphase having an input current sample greater than the average of theinput current samples to decrease the input current provided to thephase.

Each phase may include an inductor having a same inductor value andtolerance. The intervals may initially be the same.

A system for balancing phase currents of a plurality of phases of amultiphase converter is provided. The system includes a controller and acurrent sensor. The controller is configured to alternately connect thephases during respective intervals to an input current. The currentsensor is configured to sample, at a node of the multiphase converterthat is common to the phases, the input current provided to the phasesto obtain respective input current samples for the phases. Thecontroller is further configured to adjust the intervals to minimizeinequality of the input current samples.

A converter for converting DC voltage levels includes a plurality ofphases, a controller, and a current sensor. The phases are connected inparallel to a common node. The controller is configured to alternatelyconnect the phases during respective intervals to an input current atthe common node. The current sensor is connected to the common node andconfigured to sample the input current provided to the phases to obtainrespective input current samples for the phases. The controller isfurther configured to adjust the intervals to minimize inequality of theinput current samples.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a converter system having a multiphase DC/DCconverter and an associated controller, a schematic of the converter anda block diagram of the controller being shown in FIG. 1, the converterbeing depicted in FIG. 1 as a 4-phase converter;

FIG. 2A illustrates a graph depicting a simulation of unbalancedcurrents of the phases of the converter over a given time, the converterbeing a 3-phase converter having three unbalanced phase currents in thissimulation;

FIG. 2B illustrates a graph depicting synchronous trigger signalsgenerated by the controller for sampling the input currents from theinput of the converter respectively inputted to the phases of theconverter at respective time instants over the given time;

FIG. 2C illustrates a graph depicting the input currents respectivelyinputted to the phases of the converter over the given time;

FIG. 3 illustrates a flowchart depicting operation of a system andmethod for balancing the currents of the phases of the converter; and

FIG. 4 illustrates a block diagram depicting operation of the balancealgorithm processor of the controller for balancing the currents of thephases of the converter.

DETAILED DESCRIPTION

Detailed embodiments of the present invention are disclosed herein;however, it is to be understood that the disclosed embodiments aremerely exemplary of the invention that may be embodied in various andalternative forms. The figures are not necessarily to scale; somefeatures may be exaggerated or minimized to show details of particularcomponents. Therefore, specific structural and functional detailsdisclosed herein are not to be interpreted as limiting, but merely as arepresentative basis for teaching one skilled in the art to variouslyemploy the present invention.

Referring now to FIG. 1, a converter system 10 having a multiphase DC/DCconverter 12 and a controller 14 is shown (“DC” stands for directcurrent). Converter 12 is operable for converting a DC voltage level toanother DC voltage level. Controller 14 controls the operation ofconverter 12 to have the converter convert a DC voltage level to anotherDC voltage level.

In FIG. 1, a schematic of converter 12 and a block diagram of controller14 are shown. Converter 12 is an n-phase converter, where n is aninteger greater than one. As an example, converter 12 is depicted inFIG. 1 as being a 4-phase converter.

An input 16 of converter 12 is connected to a DC voltage source 20. Anoutput 18 of converter 12 is connected to a load 22. Converter 12includes a DC-link capacitor 24 connected in parallel to DC voltagesource 20. DC-link capacitor 24 is thus part of input 16 of converter12. Converter 12 includes an output capacitor 26 connected in parallelto load 22. Output capacitor 26 is thus part of output 18 of converter12.

Converter 12 includes multiple “phases” (i.e., the converter is a“multiphase converter”). Each phase is a converter circuit. The phases(i.e., the converter circuits) function for converter 12 to convert aninput DC voltage into an output DC voltage. Converter 12 includes fourphases as the converter as shown in FIG. 1 is a 4-phase converter. Thefour phases include a first phase 28 a, a second phase 28 b, a thirdphase 28 c, and a fourth phase 28 d (collectively “phases 28”). Phases28 are connected in parallel between input 16 and output 18 of converter12. The parallel connection of phases 28 is used to share powertransference, resulting in component size reduction and efficiency (costimprovement).

Phases 28 have the same layout. Thus, for brevity, only the layout offirst phase 28 a will be described in further detail. First phase 28 aincludes a switch arrangement connected in parallel with DC-linkcapacitor 24. The switch arrangement includes a first (upper) switch 30and a second (lower) switch 32. Switches 30 and 32 are connected inseries. Switches 30 and 32 are semiconductor devices (e.g., transistorssuch as MOSFETs as indicated in FIG. 1). As known to those of ordinaryskill in the art, lower switch 32 is used in place of a diode to providesynchronous rectification. First phase 28 a further includes an inductor34. Inductor 34 is electrically connected at one end betweenserially-connected switches 30 and 32 and at another end to output 18 ofconverter 12. Thus, as described and as illustrated in FIG. 1, phases 28each include their own switch arrangement having first and secondswitches 30 and 32 and their own inductor 34.

Controller 14 controls the operation of phases 28 for converter 12 toconvert an input DC voltage at input 16 of the converter to an output DCvoltage at output 18 of the converter. Particularly, controller 14controls the switches 30 and 32 of phases 28 to turn on the phases atrespective intervals over successive switching periods. The intervalsare spaced-apart such that only one phase is turned on at a time (e.g.,second phase 28 b, third phase 28 c, and fourth phase 28 d are turnedoff while first phase 28 a is turned on; first phase 28 a, third phase28 c, and fourth phase 28 d are turned off while second phase 28 b isturned on; etc.).

This “turned on” and “turn off” of phases 28 is in relation to input 16of converter 12. Particularly, upper switch 30 of a phase is switched onand lower switch 32 of the phase is switched off while the phase isturned on. Current from input 16 flows to a phase while the phase isturned on. Conversely, lower switch 32 of a phase is switched on andupper switch 30 of the phase is switched off while the phase is turnedoff. Current from input 16 does not flow to a phase while the phase isturned off. The current flowing through a phase while the phase isturned off is the current from the inductor of the phase.

In sum, the current from input 16 flowing to a phase while the phase isturned on with the other phases being turned off is the current flowingthrough the phase (i.e., the input current=the phase current;i_(input)=i_(phase)).

In one type of operation, controller 14 controls the operation of phases28 for converter 12 to convert a high DC input voltage at input 16 ofthe converter to a low DC output voltage at output 18 of the converter.As such, converter 12 is a step-down or “buck” converter. For example,DC voltage source 20 at input 16 is a 48 VDC voltage source and theoutput DC voltage at output 18 is to be a 12 VDC voltage output.Controller 14 controls the operation of phases 28 for converter 12 toconvert the 48 VDC voltage input to the 12 VDC voltage output.

Converter 12 is bi-directional. Thus, output 18 may be the “input” ofconverter 12 and input 16 may be the “output” of the converter. In thiscase, controller 14 controls the operation of phases 28 for converter 12to convert a low DC input voltage at output 18 to a high DC outputvoltage at input 16. As such, converter 12 is a step-up or “boost”converter. For example, a DC voltage source at output 18 is a 12 VDCvoltage source and the output DC voltage at input 16 is to be a 48 VDCvoltage output. Controller 14 controls the operation of phases 28 forconverter 12 to convert the 12 VDC input voltage at output 18 to the 48VDC output voltage at input 16. The 12 VDC and 48 VDC values arestrictly examples. As described herein, converter 12 may be operated asa more general buck-boost converter for any but practically limitedvoltage conversion.

As indicated in FIG. 1, controller 14 includes various electricalprocessors, circuits, drivers, etc. for carrying out various controlfunctions. Particularly, controller 14 includes a central processingunit (CPU) 36 which functions as a central command and processing point.Controller 14 further includes a plurality of phase drivers 38 a, 38 b,38 c, and 38 d (collectively “phase drivers 38”). Phase drivers 38 arerespectively associated with phases 28. Phase driver 38 a drivesswitches 30 and 32 of first phase 28 a to turn these switches on andoff; phase driver 38 b drives switches 30 and 32 of second phase 28 b toturn these switches on and off; etc.

As described above, phases 28 include their own switch arrangementhaving first and second switches 30 and 32 and their own inductor 34. Asphases 28 have the same layout, inductors 34 of the phases have the samegiven inductor value and tolerance (e.g., “x” Henrys ±5%). (In otherembodiments, inductors 34 of phases 28 are designed with differentinductor values with appropriate control being implemented by controller14 to account for the different inductor values while controlling theoperation of the phases for converter 12 to convert voltages.)

Under the assumption that inductors 34 have the same inductor value,controller 14 switches phases 28 on with the same duty cycle incontrolling the operation of the phases for converter 12 to convertvoltages. (The duty cycle is the duration of an interval that a phase 28is turned on relative to the duration of a switching period for all thephases.) Phases 28 turned on with the same duty cycle have the same(i.e., balanced) currents when inductors 34 have the same inductorvalue.

However, due to different component values (e.g., tolerance) and/oraging, inductors 34 have different inductor values. Consequently, phases28 will have different (i.e., unbalanced) currents while controller 14switches phases 28 on with the same duty cycle. What is needed is forcontroller 14 to individually adjust the duty cycles to switch phases 28on with different duty cycles so that the phases will have balancedcurrents when inductors 34 have different inductor values. The durationsof the different duty cycles are to be appropriately adjustedindividually for phases 28 to have balanced currents.

In accordance with embodiments of the present invention, convertersystem 10 includes further features and aspects which function tobalance the current of phases 28 of converter 12 while the converter isconverting voltage levels. These features and aspects function to havecontroller 14 switch phases 28 on with different duty cycles so that thephases will have balanced currents when inductors 34 have differentinductor values (i.e., the phase currents will be balanced even thoughthe behavior of the phases differ from one another).

In this regard, converter 12 further includes a current shunt 46 and anassociated operational amplifier 48 and controller 14 further includes acurrent processor 40, a balancing algorithm processor 42, and a control& synchronization (“C&S”) processor 42. Current shunt 46 is connected atone end to input 16 of connector 12 and is connected at another end to acommon node 50 of phases 28. Thus, current from input 16 (i.e., “theinput current”) flowing to a phase 28 while the phase is turned on (andwhile the other phases are turned off) flows through current shunt 46and then flows through phase 28. That is, the input current flowsthrough current shunt 46 and then flows through phase 28. No othercurrent flows through phase 28 during this time. Thus, the inputcurrent, the current flowing through current shunt 46, and the currentflowing through phase 28 are the same current. Accordingly, the currentflowing through current shunt 46 is the same as each of the inputcurrent and the current flowing through phase 28 (i.e.,i_(input)=i_(shunt)=i_(phase)). Amplifier 48 is arranged to generate avoltage signal indicative of the current flowing through current shunt46.

Controller 14 is arranged to receive from amplifier 48 the voltagesignal indicative of the current flowing through current shunt 46.Particularly, current processor 40 is in communication with amplifier 48to receive this voltage signal. Current processor 40 processes thisvoltage signal to determine a value of the current flowing throughcurrent shunt 46. Current processor 40 provides this value to CPU 36. Asnoted, the current flowing through current shunt 46 is the currentflowing through a given phase 28 while the phase is turned on (and whilethe other phases are turned off). Further, this current is the inputcurrent inputted from input 16 of converter 12 to the given phase 28.Accordingly, the value of the current flowing through current shunt 46is the value of the input current inputted to the given phase 28 and thevalue of the current flowing through the given phase.

Referring now to FIGS. 2A, 2B, 2C, with continual reference to FIG. 1,operation carried out by converter system 10 in accordance withembodiments of the present invention to balance the current of phases 28of converter 12 while the converter is converting voltage levels will bedescribed. For simplicity, FIGS. 2A, 2B, and 2C are based on converter12 being a 3-phase converter (e.g., the converter having only first,second, and third phases 28 a, 28 b, and 28 c).

FIG. 2A illustrates a graph depicting a simulation of unbalanced phasecurrents over a given time. (A “phase current” is the current flowingthrough a phase.) The unbalanced phase currents include a first phasecurrent 52 a of first phase 28 a, a second phase current 52 b of secondphase 28 c, and a third phase current 52 c of third phase 28 c. As shownin FIG. 2A, phase currents 52 a, 52 b, 52 c (collectively “phasecurrents 52”) are unbalanced (i.e., two or more phase currents havedifferent values at given time instants). Operation carried out byconverter system 10 causes phase currents 52 to be balanced (i.e., thephase currents will have substantially the same value all the time)during steady-state.

FIG. 2B illustrates a graph depicting synchronous trigger signalsgenerated by controller 14 for sampling the input currents respectivelyinputted from input 16 of converter 12 to phases 28 at respective timeinstants over the given time; and FIG. 2C illustrates a graph depictingthe input currents respectively inputted to phases 28 over the giventime.

As shown in the graph of FIG. 2C, the input currents include a firstinput current 56 a, a second input current 56 b, and a third inputcurrent 56 c (collectively “input currents 56”). As described herein,controller 14 alternately switches on phases 28 to cause first inputcurrent 56 a to flow to first phase 28 a during a first interval, secondinput current 56 b to flow to second phase 28 b during a secondinterval, and third input current 56 c to flow to third phase 28 cduring a third interval. The intervals are spaced-apart such that onlyone of input currents 56 flows to a phase 28 at a time. As indicated byinput currents 56 having the same width along the time axis of the graphin FIG. 2C, the intervals have the same duration. As such, the dutycycle is the same for all phases 28. The first, second, and thirdintervals occur during a switching period and, as indicated by therepeating pattern of input currents 56, the switching period continuallyrepeats.

As the duty cycles are the same, phase currents 52 would be balanced ifphases 28 behaved the same (e.g., if inductors 34 had the same inductorvalue). However, phase currents 52 are unbalanced as shown in the graphof FIG. 2A due to phases 28 behaving differently. The same duty cyclesfor differently behaving phases 28 result in the unbalanced phasecurrents such as shown in the graph of FIG. 2A.

As noted above, controller 14 operates to individually adjust the dutycycles to switch phases 28 on with different duty cycles so that thephases have balanced currents when the phases behave differently. Thesynchronous trigger signals generated by controller 14 for samplinginput currents 56 are part of this operation. As shown in the graph ofFIG. 2B, the trigger signals include a first trigger signal 54 a, asecond trigger signal 54 b, and a third trigger signal 54 c(collectively “trigger signals 54”). C&S processor 44 of controller 14,under the command of CPU 36 of the controller, alternately generatestrigger signals 54. C&S processor 44 alternately generates triggersignals 54 in conjunction with the switching of phases 28 according to aschedule determined by the CPU. The schedule is customized to provide along enough duration to allow analog-to-digital processing conversion ofsampled input currents 56.

Current processor 40 of controller 14 receives trigger signals 54 asthey are generated. Upon receiving a trigger signal 54, currentprocessor 40 samples the voltage signal being generated by amplifier 48of converter 12. As described herein, this voltage signal is indicativeof the current flowing through current shunt 46; the current flowingthrough the current shunt is equal to each of the input current and thephase current; and thus, this voltage signal is also indicative of eachof the input current and the phase current. In this way, input currents56 are sampled.

As shown in FIG. 2B in conjunction with FIG. 2C, first trigger signal 54a is for sampling first input current 56 a inputted to first phase 28 aat a first time instant t₁, second trigger signal 54 b is for samplingsecond input current 56 b inputted to second phase 28 b at a second timeinstant t₂, and third trigger signal 54 c is for sampling third inputcurrent 56 c inputted to third phase 28 c at a third time instant t₃.The values of sampled input currents 56 include a first value of firstinput current 56 a at the first time instant t₁, a second value ofsecond input current 56 b at the second time instant t₂, and a thirdvalue of third input current 56 c at the third time instant t₃.

Current processor 40 provides the values of sampled input currents 56 toCPU 36 and balancing algorithm processor 42 of controller 14. Asdescribed, the first value of first input current 56 a is the value ofphase current 52 a of first phase 28 a; the second value of second inputcurrent 56 b is the value of phase current 52 b of second phase 28 b;and the third value of third input current 56 c is the value of phasecurrent 52 c of third phase 28 c.

Balancing algorithm processor 42 processes the values of phase currents52 to determine how to balance the phase currents when they areunbalanced. For example, balancing algorithm processor 42 determines anaverage of the values of phase currents 52 and determines the differencefrom the average for the phase currents. The difference from the averagefor each phase current 52 is to be added or subtracted for that phasecurrent to be at the average. For example, if the first, second, andthird phase currents 52 a, 52 b, and 52 c respectively have the valuesof 33, 42, and 45 amps, then the average is 40 amps ((33+42+45)/3=40).Accordingly, for phases currents 52 to be balanced, first phase current52 a having the value of 33 amps is to be increased by 7 amps; secondphase current 52 b having the value of 42 amps is to be decreased by 2amps; and third phase current 52 c having the value of 45 amps is to bedecreased by 5 amps. Upon these changes being made, phase currents 52will all be 40 amps and therefore will be balanced.

Balancing algorithm processor 42 provides its determination on how tobalance phase currents 52 to CPU 36. CPU 36 adjusts duty cyclesindividually for phases 28 to balance phase currents 52. As describedherein, the duty cycle is the duration during which the input currentflows to a phase. A larger duty cycle generates more input currentwhereas a smaller duty cycle generates less input current. Thus, alarger duty cycle results in more input current flowing to a phasewhereas a smaller duty cycle results in less input current flowing tothe phase. CPU 36 individually adjusts the duty cycles for phases 28 toeither increase or decrease (or maintain) the input currents flowing tothe phases. CPU 36 determines the duty cycle adjustments which willresult in phases 28 having balanced phase currents 52.

For instance, in the example above where first, second, and third phasecurrents 52 a, 52 b, and 52 c respectively have the values of 33, 42,and 45 amps, CPU 36 increases the duty cycle for first input current 56a so that the value of first phase current 52 a increases from 33 to 40amps; slightly decreases the duty cycle for second input current 56 b sothat the value of second phase current 52 b decreases from 42 to 40amps; and decreases the duty cycle for third input current 56 c so thatthe value of third phase current 52 c decreases from 45 to 40 amps. Inthis way, phases 28 are respectively associated with individualizedinput current duty cycles so that the phase currents 52 will bebalanced.

CPU 36 provides commands indicative of the individualized input currentduty cycles to C&S processor 44. C&S processor 44 controls phase drivers38 accordingly to implement the individualized input current dutycycles.

Referring now to FIG. 3, with continual reference to FIGS. 1, 2A, 2B,and 2C, a flowchart 60 depicting operation of a system and method forbalancing phase currents 52 is shown. For simplicity, the operation offlowchart 60 is based on a 2-phase converter having first phase 28 a andsecond phase 28 b. The operation begins with the input current beingsampled at a first time t₁ while first phase 28 a is turned on, asindicated in block 62. The phase current of first phase 28 a isdetermined to be the sampled input current at the first time t₁ (i.e.,i_(phase1)=i_(input_t1)), as indicated in block 64. The input current isthen sampled at a second time t₂ while second phase 28 b is turned on,as indicated in block 66. The phase current of second phase 28 b isdetermined to be the sampled input current at the second time t₂ (i.e.,i_(phase2)=i_(input_t2)) as indicated in block 68.

The average of the phase currents is determined, as indicated in block70. The ±value difference from the average for each of the phase currentof first phase 28 a and the phase current of second phase 28 bdetermined, as indicated in block 72. The input current duty cycle forfirst phase 28 a is adjusted based on the ±value difference from theaverage for the phase current of the first phase and the input currentduty cycle for second phase 28 b is adjusted based on the ±valuedifference from the average for the phase current of the second phase,as indicated in block 74. The adjustments in the input current dutycycles result in the phase currents being balanced (i.e.,i_(phase1)=i_(phase2)), as indicated in block 76.

Referring now to FIG. 4, with continual reference to FIG. 1, a blockdiagram depicting operation of balance algorithm processor 42 ofcontroller 14 for balancing the currents of phases 28 of converter 12 isshown. As shown in FIG. 4, balance other than processor 42 includes ananalog-to-digital converter (ADC) 80 and a calculator 82. ADC 80 samplesthe input currents in response to receiving the trigger signals from C&Sprocessor 44 of controller 14. ADC 80 provides the sampled inputcurrents to calculator 82. Calculator 82 determines an average of thesampled input currents. As described herein, the sampled input currentsare the phase currents, respectively, at the time the sampled inputcurrents are sampled.

As shown in FIG. 4, balance algorithm processor 42 further includescircuitry such as proportional integral (PI) devices, generallyindicated that 84, for determining how the input current duty cyclesshould be adjusted so that the phase currents will become balanced. Thiscircuitry may be alternatively a part of CPU 36 for the CPU to makethese determinations as has been described above.

With reference to FIGS. 2B and 2C, the balance algorithm is executed ina slow cycle. The sampling of the currents is every “m” cycles to allowfor ADC 80 to process each sample. The balancing algorithm may beexecuted after “2m” cycles of the current since there is one sample foreach of the multiple currents sampled. Duty cycle tuning is not higherthan ±1% to avoid instabilities (fine tuning). The balancing is used insteady-state, one start-up is finished.

As described, systems and methods to avoid unbalancing currents betweenphases in accordance with embodiments of the present invention employ acommon current loop having current shunt. The systems and methodsprovide a novel measurement and processing algorithm which takes thesynchronization from each phase activation signal to selectively samplethe common current measurement. The synchronized samples enableidentifying each phase share and the required adjustment of each phaseduty cycle ratio. As further described, the measurement is done at thehigh-voltage side of the multiphase converter, which is in series with aDC-link capacitor. Only one current shunt sensor and only oneoperational amplifier, as opposed to respective current shunt sensorsand operational amplifiers of the multiple phases, is employed by thesystems and methods. As further described, the systems and methods usethe current shunt sensor to control the total current (power) flowtogether with the phase balancing.

Benefits of systems and methods to avoid unbalancing currents betweenphases in accordance with embodiments of the present invention includethe following. A single current loop which results in a smaller, cheapersystem. The smaller, cheaper system can have just one current shuntsensor and one operational amplifier and therefore can have lesscomponents to place in the printed circuit board (PCB). Less CPU loadrequirements as a relatively little more complex algorithm is simplerthan three separate and parallel processing flows. This makes availablethe option for a smaller (cheaper) controller. The multiphase converterhas higher efficiency due to less losses. The high-voltage input stagehas lower current than low-voltage output stages (approximately 4-timesfor 48V-12V converter). Thus, with same resistance (accuracy) shuntpower dissipation (I2R) is smaller in the input stage than in then-phases output (combined). Balanced phase aging, like in thetraditional system with one current control loop per phase, is abenefit. The method and system can be used in other switched systemslike on-board chargers (OBC) or inverters, provided they use amulti-phase strategy.

While exemplary embodiments are described above, it is not intended thatthese embodiments describe all possible forms of the present invention.Rather, the words used in the specification are words of descriptionrather than limitation, and it is understood that various changes may bemade without departing from the spirit and scope of the presentinvention. Additionally, the features of various implementingembodiments may be combined to form further embodiments of the presentinvention.

1. A method for balancing phase currents of a plurality of phases of amultiphase converter, the method comprising: alternately connecting thephases during respective intervals to an input current; generatingtrigger signals at successive time instants respectively for the phases,wherein the trigger signals are synchronous in that the trigger signalsare generated at a same time following the connection of the phases tothe input current; sampling, at the time instants in response to thetrigger signals, at a node of the multiphase converter that is common tothe phases, the input current provided to the phases to obtainrespective input current samples for the phases; and while the inputcurrent samples are unequal, adjusting the intervals based only ondifferences between the input current samples to minimize inequality ofthe input current samples. 2-3. (canceled)
 4. The method of claim 1wherein: the node of the multiphase converter that is common to thephases is connected to a DC-link capacitor of the multiphase converter.5. The method of claim 1 wherein: adjusting the intervals includesincreasing the interval for a phase having an input current sample lowerthan an average of the input current samples to increase the inputcurrent provided to the phase; and adjusting the intervals includesdecreasing the interval for a phase having an input current samplegreater than the average of the input current samples to decrease theinput current provided to the phase.
 6. The method of claim 1 wherein:each phase includes an inductor, the inductors of the phases have a sameinductor value and tolerance.
 7. The method of claim 1 wherein: theintervals initially are the same.
 8. A system for balancing phasecurrents of a plurality of phases of a multiphase converter, the systemcomprising: a controller configured to alternately connect the phasesduring respective intervals to an input current from a power source andto generate trigger signals at successive time instants respectively forthe phases, wherein the trigger signals are synchronous in that thetrigger signals are generated at a same time following the connection ofthe phases to the input current; a current sensor configured to sample,at the time instants in response to the trigger signals, at a node ofthe multiphase converter that is common to the phases, the input currentprovided to the phases to obtain respective input current samples forthe phases, wherein the current sensor includes a current shuntconnected in series between the power source and the node; and whereinthe controller is further configured to adjust the intervals based onlyon differences between the input current samples to minimize inequalityof the input current samples. 9-10. (canceled)
 11. The system of claim 8wherein: the node of the multiphase converter that is common to thephases is connected to a DC-link capacitor of the multiphase converter.12. The system of claim 8 wherein: the controller is further configuredto adjust the intervals includes increasing the interval for a phasehaving an input current sample lower than an average of the inputcurrent samples to increase the input current provided to the phase; andthe controller is further configured to adjust the intervals includesdecreasing the interval for a phase having an input current samplegreater than the average of the input current samples to decrease theinput current provided to the phase.
 13. The system of claim 8 wherein:each phase includes an inductor, the inductors of the phases have a sameinductor value and tolerance.
 14. The system of claim 8 wherein: theintervals initially are the same.
 15. A converter for converting DCvoltage levels, comprising: a plurality of phases connected in parallelto a common node; a power source configured to provide an input currentto the common node; a controller configured to alternately connect thephases during respective intervals to the input current at the commonnode and to generate trigger signals at successive time instantsrespectively for the phases, wherein the trigger signals are synchronousin that the trigger signals are generated at a same time following theconnection of the phases to the input current; a current sensor having acurrent shunt connected in series between the power source and thecommon node, the current sensor configured to sample, at the timeinstants in response to the trigger signals, the input current providedto the phases to obtain respective input current samples for the phases;and the controller is further configured to adjust the intervals basedonly on differences between the input current samples to minimizeinequality of the input current samples. 16-17. (canceled)
 18. Theconverter of claim 15 further comprising: a DC-link capacitor connectedto the common node.
 19. The converter of claim 15 wherein: thecontroller is further configured to adjust the intervals includesincreasing the interval for a phase having an input current sample lowerthan an average of the input current samples to increase the inputcurrent provided to the phase; and the controller is further configuredto adjust the intervals includes decreasing the interval for a phasehaving an input current sample greater than the average of the inputcurrent samples to decrease the input current provided to the phase. 20.The converter of claim 15 wherein: each phase includes an inductor, theinductors of the phases have a same inductor value and tolerance. 21.The method of claim 1 wherein: each time instant at which acorresponding trigger signal is generated occurs after M cycles of thephases have been alternately connected to the input current, wherein Mis an integer greater than one.
 22. The system of claim 8 wherein: eachtime instant at which a corresponding trigger signal is generated occursafter M cycles of the phases have been alternately connected to theinput current, wherein M is an integer greater than one.
 23. Theconverter of claim 15 wherein: each time instant at which acorresponding trigger signal is generated occurs after M cycles of thephases have been alternately connected to the input current, wherein Mis an integer greater than one.